PDF

postscript

bibtex

Notice for the last references

• Topic distribution :
• Online papers :
• Theses :
• References :

 
BY TOPICS

FPGA modeling and basic tools :

[39] [27][29]

Object oriented high level synthesis :

[2][32][20] [21][30][31][40]

Low level synthesis :

[37][36]

Parallel reconfigurable architectures and ArMen :

[33][23][18][11] [16][25]

System on chips, new technologies :

[8][12][43]

Tools, languages and algorithms for reconfigurable architectures :

[44][17] [3] [7] [24]

Application to distributed simulation :

[4] [5]

Fast prototyping and tools for code generation :

[19][42]

Misc :

[13][34][45]

Theses  :

[28] [41] [38] [6] [46] [15] [9] [22]

Acknowledgements

PAPERS

2007

[*] Modeling Sensor Networks as Concurrent Systems (poster), Cornelia Amariei, Ciprian Teodorov, Erwan Fabiani, and Bernard Pottier, INSS'07

[*] Investigating sensor networks with concurrent sequential processes and Smalltalk (demonstration), Cornelia Amariei, Ciprian Teodorov, INSS'07

[*] Coordinated concurrent memory accesses on a reconfigurable multimedia processor, Samar Yazdani, Joel Cambonie and Bernard Pottier, ReCoSoC'07 (LIRMM, Montpellier)

[*] An integrated platform for heterogeneous reconfigurable computing, Bernard Pottier, Jalil Boukhobza and Thierry Goubier, ERSA'07 (LasVegas)

2006

[*] The case study of block turbo decoders on a framework for portable synthesis on FPGAs, Catherine Dezan, Christophe Jego, Bernard Pottier, Christophe Gouyen, Loic Lagadec, HICSS-MOCHA

[*] Synthèse portable pour micro-architectures à grain fin, application aux turbo décodeurs et nano-fabriques , Catherine Dezan, Erwan Fabiani, Christophe Gouyen, Loic Lagadec, Bernard Pottier, Caaliph Andriamisaina and Alix Poungou, TSI (Hermes, in french)

2005

[2] Synthèse abstraite d'éléments de turbo-décodeurs en bloc pour circuits reconfigurables, Caaliph Andriamisaina, Catherine Dezan, Christophe Jego et Bernard Pottier, Sympa'2005

[35] Madeo, une approche MDA pour la programmation et la synthèse d'architectures reconfigurables, Sébastien Lebeux et Loic Lagadec , Sympa'2005

[43] Du reconfigurable aux nano-fabriques : composants nano-électroniques et outils de modélisation, Alix Poungou, Erwan Fabiani, Loic Lagadec et Bernard Pottier, Sympa'2005

2004

[8] Compiler and system techniques for SOC distributed reconfigurable accelerators, Joël Cambonie, Sylvain Guérin, Ronan Keryell, Loïc Lagadec, Bernard Pottier, Olivier Sentieys, Bernt Weber et Samar Yazdani SAMOS, 2004

[12] Abstract execution mechanisms in a synthesis framework, Catherine Dezan, Erwan Fabiani, Loic Lagadec, Bernard Pottier, Alix Poungou et Samar Yazdani , Workshop Non-Silicon Computations (NSC3)

2003

[20] Intermediate level components for reconfigurable platforms, Erwan Fabiani, Christophe Gouyen, Bernard Pottier , SAMOS, 2003

[26] Outils génériques pour le reconfigurable: Applications aux architectures commerciales, Christophe Gouyen and Loïc Lagadec Renpar/CFSE/SYMPAAA 2003, (INRIA, GDR ARP)

[1] DRUM: une unité reconfigurable intégrée sur plateforme multiprocesseurs hétérogène, Sumit Ahuja, Love Kothari, Erwan Fabiani et Bernard Pottier Renpar/CFSE/SYMPAAA 2003, (INRIA, GDR ARP)

2002

[31] A LUT based approach for high level synthesis on FPGAs, Loic Lagadec, Bernard Pottier, Oscar Villellas, Erwan Fabiani, Catherine Dezan, IWLAS, 2002

[32] An LUT based high level synthesis framework for reconfigurable architectures Loic Lagadec, Bernard Pottier, Oscar Villellas, SAMOS, 2002 + chapter in Dekker ed.

[14] Simulation distribuée de systèmes VHDL: étude de cas, C.Dezan and A.Plantec , Rapport de contrat, AS, UBO

2001

[39] Outils génériques pour les architectures reconfigurables, L.Lagadec, SYMPA'7 (Paris)

[27] Placing, Routing and Editing Virtual FPGAs, L. Lagadec and D. Lavenier and E. Fabiani and B. Pottier, FPL2001 (Belfast)

[45] Simulation distribuée de systèmes VHDL, H.Roussain, , J.Regnault, B. Pottier, C.Dezan, A.Plantec et L.Lemarchand , Rapport d'étude, AS, UBO

2000

[30] Compiling for reconfigurable architectures, a Reed-Solomon error correction case study, Loic Lagadec, Bernard Pottier, Oscar Villellas, Technical report

[29] Object-oriented meta tools for reconfigurable architectures, Loic Lagadec and Bernard Pottier, SPIE Photonics East (Boston)

1999

[21] Embedded system modeling and synthesis in OO environments. A smart-sensor case study, German Fabregat and German Leon and Olivier Le Berre and Bernard Pottier, Compiler and Architecture Support for Embedded Systems - CASES'99 (Washington DC)

[37] Parallel Performance Directed Technology Mapping for FPGA, L. Lemarchand, IEEE Southwest Symposium on Mixed-Signal Design (Tucson)

[13] Object Oriented Approach For Modeling Digital Circuits, Catherine Dezan, Loic Lagadec and Bernard Pottier, IEEE Microelectronic Systems Education, (Washington DC)

1998

[19] The Step Standard as an Approach for Design and Prototyping, A. Plantec et V. Ribaud, Rapid System Prototyping, RSP-9,

1997

[36] Parallel synthesis of large combinational circuits for FPGAs, L. Lemarchand, HPCN Europe'97 (Vienne)

1996

[40] Smalltalk blocks revisited, a logic generator for FPGAs, José-Luis Llopis and Bernard Pottier, FCCM'96 (Napa)

[42] Data Management: From EXPRESS Schemata To User Interface, Alain Plantec et Vincent Ribaud, Journal of Computing and Information

1995

[3] Using FPGAs as control support in MIMD executions , C. Beaumont, FPL'95 (Oxford)

1994

[17] Global Control Synthesis for an MIMD/FPGA Machine, P. Dhaussy and J.-M. Filloque and B. Pottier and S. Rubini, IEEE FCCM'94 (Napa),

[10] Parallel Grep, J. Champeau and L. Le Pape and B. Pottier, $3^{rd}$ International Workshop on Algorithms and Parallel VLSI (Leuwen),

[16] ArMen: an FPGA-based parallel architecture, P. Dhaussy and J.-M. Filloque and B. Pottier and S. Rubini, IPPS-8 (Cancun),

[5] Reconfigurable technology: An innovative solution for parallel discrete event simulation support, C. Beaumont and P. Boronat and J. Champeau and J.-M. Filloque and B. Pottier, ACM/IEEE Parallel and Distributed Simulation PADS'94 (Edinburgh),

[4] On FPGA as a new Hardware Support for Parallel Discrete Event Simulation,, C. Beaumont and P. Boronat and J. Champeau and J.-M. Filloque and B. Pottier, SMS TPE'94 (Moscou),

[11] Flexible Parallel FPGA-based Architectures with ArMen,, J. Champeau and L. Le Pape and B. Pottier and S. Rubini and E. Gautrin and L. Perraudeau, $37^{th}$ Annual Hawaii International Conference on System Sciences (ACM-IEEE),

1993

[25] Machines parallèles et logique reconfigurable, J.-M. Filloque and B. Pottier, AFCET'93 (Versailles)

[44] Fine grain parallelism on an MIMD machine using FPGAs, F. Raimbault and D. Lavenier and S. Rubini and B. Pottier, IEEE FCCM'93 (Napa),

[18] , Specification and Compilation of Distributed Algorithms for the ArMen Machine, P. Dhaussy and S. Rubini, SMS TPE'93 (St Petersbourg)

1992

[23] Le contrôle global sur une architecture à couche logique reconfigurable, J.-M. Filloque and P. Dhaussy, RENPAR-4 (Lille),

[34](short paper)  [34](paper)
An Object-Oriented Environment for Specification and Concurrent Execution of Genetic Algorithms, L. Le Marchand and A. Plantec and B. Pottier and S. Zanati, OOPSLA'92 (poster session), (Vancouver)

1991

[7] Implementing cellular automata on the ArMen machine, K. Bouazza and J. Champeau and P. Ng and B. Pottier and S. Rubini, Workshop on Algorithms and Parallel VLSI Architectures II (Bonas),

[24] Efficient Global Computation on a Processor Network with Programmable Logic, J.-M. Filloque and E. Gautrin and B. Pottier, PARLE'91 (Eindhoven),

1989

[33] High Rate Sigma Filtering, Feasibility Studies on Processors Networks, D. Lavenier et P. Pottier, IFIP Workshop Parallel Architectures on Silicon, (Grenoble).

THÈSES (EN FRANÇAIS!)

(links to thesis documents)

[28] Abstraction, modélisation et outils de CAO pour les architectures reconfigurables, Loic Lagadec, Université de Rennes I, France, 2000.

[41] Exploitation de la norme STEP pour la spécification et la mise en oeuvre de générateurs de code, Alain Plantec, Université de Rennes I, France, 1999.

[38] Parallélisation par partitionnement pour la synthèse logique combinatoire sur FPGA à base de LUT, Laurent Lemarchand, Université de Rennes I, France, 1999.

[6] Simulation distribuée: de l'application vers un support système, Christophe Beaumont, Université de Rennes I, France, 1998.

[46] Intégration des FPGA dans les architectures MIMD, Stéphane Rubini, Université de Rennes I, France, 1995.

[15] Un modèle de programmation des contrôleurs globaux, Philippe Dhaussy, Université de Rennes I, France, 1994.

[9] Synthèse d'opérateurs globaux sur lamachine ArMen, Joel Champeau, Université de Rennes I, France, 1994.

[22] Synchronisation répartie sur une machine parallèle à couche logique reconfigurable, Jean-Marie Filloque, Université de Rennes I, France, 1992.

 

ACKNOWLEDGEMENTS

(links to bibliography entries)

Many of these papers describe works leaded in cooperation with other labs:

API/COSI projects at IRISA (Rennes):

[33][24][44] [11] [27],

ENST-Bretagne (Brest), in the framework of the ArMen project:

[17] [16] [18] [23]

UJI (Castello, Spain):

[5] [4] [40][21]

Estrella meeting with UJI (enlarge)

 
Main fundings for these projects has been:

PRC/GDR C3 and ANM programs from ministry of education and research, and CNRS,

the PhD program from university of Rennes 1,

ANVAR-Bretagne,

STSI from ministry of industry, jointly with STMicroelectronics.

 

Bibliographie

1

Sumit Ahuja, Love Kothari, Erwan Fabiani, and Bernard Pottier.
DRUM: une unité reconfigurable intégrée sur plateforme multiprocesseurs hétérogène.
In Auguin, Baude, Lavenier, and Riveill, editors, Renpar/CFSE/SYMPAAA 2003, (INRIA, GDR ARP), La Colle sur Loup, oct 2003.

2

Caaliph Andriamisaina, Catherine Dezan, Christophe Jego, and Bernard Pottier.
Synthèse abstraite d'éléments de turbo-décodeurs en bloc pour circuits reconfigurables.
In Sympa'2005. GDR ARP, apr 2005.

3

C. Beaumont.
Using FPGAs as control support in MIMD executions.
In Proceedings of the workshop FPL'95, number 975 in LNCS, pages 94-103, Oxford, UK, aug 1995. Springer-Verlag.

4

C. Beaumont, P. Boronat, J. Champeau, J.-M. Filloque, and B. Pottier.
On fpga as a new hardware support for parallel discrete event simulation.
In Proceedings of the second International Workshop SMS TPE'94, pages 220-229, Moscou, CEI, sep 1994. SCS.

5

C. Beaumont, P. Boronat, J. Champeau, J.-M. Filloque, and B. Pottier.
Reconfigurable technology: An innovative solution for parallel discrete event simulation support.
In Proceedings of the workshop ACM/IEEE Parallel and Distributed Simulation PADS'94, Edinbourgh, UK, jul 1994. SCS.

6

Christophe Beaumont.
Simulation distribuée : de l'application vers un support système, Apr 1998.

7

K. Bouazza, J. Champeau, P. Ng, B. Pottier, and S. Rubini.
Implementing cellular automata on the ArMen machine.
In P. Quinton and Y. Robert, editors, Proceedings of the Workshop on Algorithms and Parallel VLSI Architectures II, pages 317-322, Bonas, France, jun 1991. Elseiver.

8

Joël Cambonie, Sylvain Guérin, Ronan Keryell, Loïc Lagadec, Bernard Pottier, Olivier Sentieys, Bernt Weber, and Samar Yazdani.
Compiler and system techniques for soc distributed reconfigurable accelerators.
In Synthesis, Architectures and Modeling of Systems (SAMOS 4), volume 3133. Springer-Verlag, 2004.

9

J. Champeau.
Synthèse d'opérateurs globaux sur la machine ArMen.
PhD thesis, Université de Rennes I, Décembre 1994.

10

J. Champeau, L. Le Pape, and B. Pottier.
Parallel Grep.
In M. Moonen and F. Catthoor, editors, $3^{rd}$ International Workshop on Algorithms and Parallel VLSI, pages 245-256, Leuven, Belgium, Août 1994. Elsevier.

11

J. Champeau, L. Le Pape, B. Pottier, S. Rubini, E. Gautrin, and L. Perraudeau.
Flexible Parallel FPGA-based Architectures with ArMen.
In $37^{th}$ Annual Hawaii International Conference on System Sciences (ACM-IEEE), Hawaii, Janvier 1994.

12

Catherine Dezan, Erwan Fabiani, Loic Lagadec, Bernard Pottier, Alix Poungou, and Samar Yazdani.
Abstract execution mechanisms in a synthesis framework .
In N. Carter and S. Goldstein, editors, Workshop Non-Silicon Computations (NSC3), (conjoint avec ISCA 2004, ACM et IEEE), Munich, Jun 2004.

13

Catherine Dezan, Loic Lagadec, and Bernard Pottier.
Object oriented approach for modeling digital circuits.
In IEEE Computer Society International Conference on Microelectronic Systems Education, jul 1999.

14

Catherine Dezan and Alain Plantec.
Simulation distribuée de systèmes VHDL: étude de cas.
Technical report, Architectures et Systèmes, UBO, Brest, Oct 2002.

15

P. Dhaussy.
Un modèle de programmation des contrôleurs globaux.
PhD thesis, Université de Rennes I, Novembre 1994.

16

P. Dhaussy, J.-M. Filloque, B. Pottier, and S. Rubini.
ArMen: an FPGA-based parallel architecture.
In H.J. Siegel, editor, $8^{th}$ International Parallel Processing Symposium (Parallel System Fair), Cancùn, Mexico, apr 1994.

17

P. Dhaussy, J.-M. Filloque, B. Pottier, and S. Rubini.
Global Control Synthesis for an MIMD/FPGA Machine.
In D. Buell and K. Pocek, editors, IEEE Workshop on FPGAs for custom computing machines (FCCM'94), pages 51-58, Napa, CA, apr 1994. IEEE Computer Society Press.

18

P. Dhaussy and S. Rubini.
Specification and compilation of distributed algorithms for the ArMen machine.
In First International Workshop SMS TPE'93, Saint Petersburg, Russia, feb 1993. Russian Academy of Sciences.

19

A. Plantec et V. Ribaud.
The step standard as an approach for design and prototyping.
In The 9th Int. workshop on Rapid System Prototyping, RSP, 1998.

20

Erwan Fabiani, Christophe Gouyen, and Bernard Pottier.
Intermediate level components for reconfigurable platforms.
In Synthesis, Architectures and Modeling of Systems (SAMOS 3), volume 3133, Samos, Grece, 2003. Springer-Verlag.

21

German Fabregat, German Leon, Olivier Le Berre, and Bernard Pottier.
Embedded system modeling and synthesis in oo environments. a smart-sensor case study.
In Guang Gao and Krishna Palem, editors, Compiler and Architecture Support for Embedded Systems (CASES'99). http://www.capsl.udel.edu/conferences/cases99, Oct 1999.

22

J.-M. Filloque.
Synchronisation répartie sur une machine parallèle à couche logique reconfigurable.
PhD thesis, Université de Rennes I, nov 1992.

23

J.-M. Filloque and P. Dhaussy.
Le contrôle global sur une architecture à couche logique reconfigurable.
In $4^{es}$ Rencontres du Parallélisme, pages 9-12, Villeneuve d'Ascq, mar 1992.

24

J.-M. Filloque, E. Gautrin, and B. Pottier.
Efficient global computation on a processor network with programmable logic.
In E. Aarts, J. van Leeuwen, and M. Rem, editors, Proceedings of PARLE'91, number 505 in LNCS, pages 55-63, Eindhoven, NL, jun 1991. Springer-Verlag.

25

J.-M. Filloque and B. Pottier.
Machines parallèles et logique reconfigurable.
In Proceedings of AFCET'93, Colloque "De la spécif ication à la validation d'architectures de systèmes parallèles", pages 143-152, Versailles, France, jun 1993. AFCET.

26

Christophe Gouyen and Loïc Lagadec.
Outils génériques pour le reconfigurable: Applications aux architectures commerciales.
In Auguin and Baude and Lavenier and Riveill, editor, Renpar/CFSE/SYMPAAA 2003, (INRIA, GDR ARP), La Colle sur Loup, Oct 2003.

27

L. Lagadec, D. Lavenier, E. Fabiani, and B. Pottier.
Placing, routing and editing virtual fpgas.
In FPL2001, LNCS, 2001.

28

Loic Lagadec.
Abstraction, modélisation et outils de CAO pour les architectures reconfigurables.
PhD thesis, Université de Rennes I, 35065 Rennes cedex, France, 2000.

29

Loic Lagadec and Bernard Pottier.
Object-oriented meta tools for reconfigurable architectures.
In Schewel J., editor, Photonics East, Boston, Ms, nov 2000. SPIE.

30

Loic Lagadec, Bernard Pottier, and Oscar Villellas.
Compiling for reconfigurable architectures, a reed-solomon error corre ction case study.
Technical report, http://penarvir.univ-brest.fr/reports/2000/TR-2000-2.pdf.zip, Dec 2000.

31

Loic Lagadec, Bernard Pottier, Oscar Villellas, Erwan Fabiani, and Catherine Dezan.
From high level functions to fpga code generation, a lut based approach.
Technical report, http://penarvir.univ-brest.fr/reports/2002/TR-2002-1.pdf, Feb 2002.

32

Loïc Lagadec, Bernard Pottier, and Oscar Villellas-Guillen.
An lut-based high level synthesis framework for reconfigurable architectures.
In S.S. Batttacharyya, E. Deprettere, and J. Teich, editors, Domain-Specific Processors : Systems, Architectures, Modeling, and Simulation, pages 19-39. Marcel Dekker, nov 2003.

33

D. Lavenier and P. Pottier.
High Rate Sigma Filtering, Feasibility Studies on Processors Networks.
In Proceedings of IFIP Workshop on Parallel Architectures on Silicon, pages 182-196, Grenoble, France, nov 1989.

34

L. Le Marchand, A. Plantec, B. Pottier, and S. Zanati.
An Object-Oriented Environment for Specification and Concurrent Execution of Genetic Algorithms.
In Sigplan Notices, editor, Addendum to OOPSLA'92, Vancouver, Canada, volume 27. ACM, oct 1992.

35

Sébastien Lebeux and Loic Lagadec.
Madeo, une approche mda pour la programmation et la synthèse d'architectures reconfigurables.
In Sympa'2005. GDR ARP, apr 2005.

36

L. Lemarchand.
Parallel synthesis of large combinational circuits for FPGAs.
In Proceedings of HPCN Europe'97, Vienne, Austria. Springer-Verlag, LNCS 1225, 1997.

37

L. Lemarchand.
Parallel performance directed technology mapping for fpga.
In Proceedings of IEEE Southwest Symposium on Mixed-Signal Design, Tucson, USA, pages 189-194, 1999.

38

Laurent Lemarchand.
Parallélisation par partitionnement pour la synthèse logique combinatoire sur FPGA à base de LUT.
PhD thesis, Université de Rennes I, 35065 Rennes cedex, France, Jan 1999.

39

L.Lagadec.
Outils génériques pour les architectures reconfigurables.
In SYMPA'7. GDR ARP, 2001.

40

José-Luis Llopis and Bernard Pottier.
Smalltalk blocks revisited, a logic generator for fpgas.
In J-M. Arnold and K. Pocek, editors, Field programmable Custom Computing Machine (FCCM'96), Napa, CA, 1996. IEEE press.

41

Alain Plantec.
Exploitation de la norme STEP pour la spécification et la mise en uvre de générateurs de code.
PhD thesis, Université de Rennes I, 35065 Rennes cedex, France, 1999.

42

Alain Plantec and Vincent Ribaud.
Data Management: From EXPRESS Schemata To User Interface.
Journal of Computing and Information, 2(1), November 1996.

43

Alix Poungou, Erwan Fabiani, Loic Lagadec, and Bernard Pottier.
Du reconfigurable aux nano-fabriques : composants nano-électroniques et outils de modélisation.
In Sympa'2005. GDR ARP, apr 2005.

44

F. Raimbault, D. Lavenier, S. Rubini, and B. Pottier.
Fine grain parallelism on an MIMD machine using FPGAs.
In D. Buell and K. Pocek, editors, Proceeding of IEEE Workshop FPGAs for Custom Computing Machines (FCCM'93), volume 3890-02, Napa, CA, apr 1993. IEEE Computer Society Press.

45

Hervé Roussain, Julien Regnault, Bernard Pottier, Catherine Dezan, Alain Plantec, and Laurent Lemarchand.
Simulation distribuée de systèmes VHDL.
Technical report, Architectures et Systèmes, UBO, Brest, Sep 2001.

46

S. Rubini.
Intégration des FPGA dans les architectures MIMD.
PhD thesis, Université de Rennes I, jul 1995.